File:MIPS Architecture (Pipelined).svg

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Original file ‎(SVG file, nominally 800 × 500 pixels, file size: 56 KB)

Summary

The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture).

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Date/TimeThumbnailDimensionsUserComment
current05:25, 5 January 2017Thumbnail for version as of 05:25, 5 January 2017800 × 500 (56 KB)127.0.0.1 (talk)The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture).
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